複選題
3. Which of the following statements are true regarding the pipeline hazards of a 5-stage MIPS CPU?
(A)The data forwarding technique passes data to the previous instructions that need the data
(B) The structural hazard happens when a required resource is busy
(C) Rearranging the instructions may solve some of the data hazards
(D)If we put the register comparator and the target address calculator at the ID stage, then 2 stalls are needed for a branch hazard
(E) If we put the register comparator and the target address calculator at the ID stage, and a comparison register is a destination of immediately preceding load instruction, then 1 stall is needed

14. Consider the liquid phase reactions shown in the schematic below carried out in a flow reactor at steady state.Keeping the reaction system isothermal, the yield of the desired product can be maximized by maintaining Keeping the reaction system isothermal, the yield of the desired product can be maximized by maintaining (A) Low concentration of A and high concentration of B (B) The high concentration of A and high concentration of B (C) Low concentration of B and low concentration of B (D) The high concentration of A and low concentration of B

15. For the irreversible elementary reaction in parallel is, the rate of disappearance of reactant A is given by (A)(k1-k2)CA (B) (k1+k2)CA (C)0.5(k1+k2)CA (D) kICA

複選題1. Given (1) an instruction has 32 bits, and (2) a cache memory with 64 blocks, 16 bytes/block, and 4-way set associative. Which of the following statements are true? (A)Byte address 1200 maps to the set number 11 (B) The index field requires 4 bits (C) The offset field is 12 bits (D)The tag field is 16 bits (E) None of the above

複選題2. Which of the following statements are true for memory hierarchy? (A)Spatial locality refers to the situation that an item tends to be referenced soon once it is referenced. (B) When increasing the size of a cache block, the miss penalty decreases (C)Increasing cache associativity decreases the utilization of a cache (D)A valid bit indicates whether the data in a block is valid or not (E) A cache block is the basic unit for the cache storage

複選題4. Given the execution time of the 5 stages of a CPU: IF 200 ps, ID 100 ps, EXE 200 ps, MEM 200 ps, WB 100 ps, which of the following statements are true? (A) The ideal cycle time of a single cycle CPU is 800 ps (B) The ideal execution time of "sw" for a single cycle CPU is 800 ps (C)The ideal cycle time of a multiple cycle CPU is 200 ps (D)The ideal execution time of "Iw" for a multiple cycle CPU is 800 ps (E) None of the above

複選題5. Given a 16-bit computer with the I-type instruction in the following format, which of the following statements are true? (A)The computer supports at most 16 operations (B) The computer has 8 registers (C) The range of the number in the immediate field (in 2's complement) is from -25 to 25-1 (D)Each register is 8-bits long (E) None of the above

複選題6. Which of the following statements are true for dynamic branch prediction? (A)Branch history table or branch prediction buffer can be implemented as a memory indexed by the lower bits of the program counter address. (B) Branch prediction buffer must have tag and address check. (C)A 2-bit dynamic branch predictor must miss twice before the prediction is changed. (D)Mis-prediction can be caused by getting the branch history of wrong branch when indexing the branch history table. (E) Correlating branch predictors assume that the behaviour of a branch would not be affected by the behaviours of other branches.

複選題7.For RISC (Reduced Instruction Set Computer), which of the following statements are true? (A)For any given level of general performance, a RISC chip will typically have far more transistors dedicated to the core logic compared with CISC (complex instruction set computer). (B) RISC allows designers to increase the size of the register set. (C)RISC usually uses uniform instruction format with with the opcode in the same bit positions in every instruction, which demands less decoding complexity. (D)RISC is not suitable for pipeline design and would decrease internal parallelism. (E) RISC usually supports more addressing modes than CISC. rs: 3 bits

複選題8. Assume that the frequency of Floating Point (FP) operations is 25% for a computer, and the average CPI (Clock Cycles Per Instruction) of FP operations is 4. The average CPI of other instructions is 1.5. By performing some enhancement on the hardware, we can reduce the average CPI of all FP operations to 2. All other factors are not changed after enhancement. Which of the followings are true? (A)The speedup for the FP operations is 2 (B) The total speedup can be computed by Amdahl's Law using the following equation: (C)The total speedup is 1.307 (D)The CPI after enhancement is 1.859 (E) The CPI before enhancement is 2.125

複選題9. About instruction level parallelism, which of the followings are true? (A)To perform loop unrolling, loop iterations must be independent with no loop-carried dependence. (B) True dependencies can be resloved by register renaming. (C)Anti-dependence occurs when instruction j writes a register or memory location that. instruction i read from, and instruction i is executed first. (D)Loop unrolling can reduce control stalls. (E) Issuing multiple instructions per cycle can not reduce ideal CPI.