3.2 Assume that a computation task contains only 100 instructions and there is no hazard for these instructions, what is the throughput of this task? What is the total latency of finishing executing this task? What is the average cycle per instruction (CPI) in this task?

2.2 If you want to achieve a speedup of 80 for a computation task using 100 processots running concurrently, what faction of the computation task can be sequential according to Amdahl's law?

2.3 For an application program running on a multi-processor system with 32 processors, it takes 200 ns to handle reference in a remote memory. Assume that this application program always bas hits in the local mem nory except for remote memor ry access involving commun nication. Proc cessors are stalled on a remote request, and the processor clock is 3.3 GHz. Assume that the base CPI (cycles per instruction) is 0.5 and all references hit in cache. How much faster is the multi-processor if there is no communicatio ion versus if 0.2% of instructions s involve remote e communication. references? Hint: compute the new CPI first. The speedup is the ratio of the two CPI values.

2.4 Assume that 25% operations of a computation task are floating-point operations and average CPI (cycles per instruction) for floating-point operations and other operations are 4.0 and 1.33 respectively. Sup ppose that 2% of the floating-poi operations in the task are floating- -point division which has CPI = 20. Assume that the two design altemnatives are to decrease the CPI of the foating- point division to 2 or the decrease the average CPI of all floating-point operations to 2.5. Compare these two design alternatives using processor performance equation. Which design choice is better? Why? Hint: compute the CPI values of different designs. e the floating-point

3.1 What is the maximun m working frequency of the above CPU?

3.3 If we want to reduc ce the pi pipelined stages from 5 to 4 by merging some of the five types of pipelined operations mentioned above, what is the best design if the spced performance is the first choice? And what is the maximun working frequency of the new design with four pipelined stages?

3.4 What is data hazard? Give an assembly language example to show one type of data hazard.

3.5 What is super-pipeline? What are the advantages and disadvantages of super-pipeline design?

4.2 Repeat the above problem for a two-way set-associative cache.

4.3 Repeat the above problem for a fully associative cache.

4.4 Compare the advantages and disadvantages of the above three different cache designs. Which one is usually used in the design of TLB (translati ation lookaside buffer)? Why?