3.4 What is data hazard? Give an assembly language example to show one type of data hazard.

2.4 Assume that 25% operations of a computation task are floating-point operations and average CPI (cycles per instruction) for floating-point operations and other operations are 4.0 and 1.33 respectively. Sup ppose that 2% of the floating-poi operations in the task are floating- -point division which has CPI = 20. Assume that the two design altemnatives are to decrease the CPI of the foating- point division to 2 or the decrease the average CPI of all floating-point operations to 2.5. Compare these two design alternatives using processor performance equation. Which design choice is better? Why? Hint: compute the CPI values of different designs. e the floating-point

3.1 What is the maximun m working frequency of the above CPU?

3.2 Assume that a computation task contains only 100 instructions and there is no hazard for these instructions, what is the throughput of this task? What is the total latency of finishing executing this task? What is the average cycle per instruction (CPI) in this task?

3.3 If we want to reduc ce the pi pipelined stages from 5 to 4 by merging some of the five types of pipelined operations mentioned above, what is the best design if the spced performance is the first choice? And what is the maximun working frequency of the new design with four pipelined stages?

3.5 What is super-pipeline? What are the advantages and disadvantages of super-pipeline design?

4.2 Repeat the above problem for a two-way set-associative cache.

4.3 Repeat the above problem for a fully associative cache.

4.4 Compare the advantages and disadvantages of the above three different cache designs. Which one is usually used in the design of TLB (translati ation lookaside buffer)? Why?

4.5 The average mem mory access time (AMAT) per instruction can be expressed as AMAT = time for a hit + miss rate *miss penalty Find the AMAT for a processor with a 1ns clock cycle time, a miss penalty of 20 clock cycles, a miss rate of 0.05 miss sses per er instru uction, and a cache ac access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the sarre and ignore other write stalls.

4.6 Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%. If 100 cycles for all misses, de etermine how m a processor has a CPI (cycle per instruction) of 2 without any memory stalls and the miss penalty is much faster a proce cessor would run with a perfect cache that never missed. Assue the frequency of all loads and stores is 36%.