4.6 Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%. If 100 cycles for all misses, de etermine how m a processor has a CPI (cycle per instruction) of 2 without any memory stalls and the miss penalty is much faster a proce cessor would run with a perfect cache that never missed. Assue the frequency of all loads and stores is 36%.

4.2 Repeat the above problem for a two-way set-associative cache.

4.3 Repeat the above problem for a fully associative cache.

4.4 Compare the advantages and disadvantages of the above three different cache designs. Which one is usually used in the design of TLB (translati ation lookaside buffer)? Why?

4.5 The average mem mory access time (AMAT) per instruction can be expressed as AMAT = time for a hit + miss rate *miss penalty Find the AMAT for a processor with a 1ns clock cycle time, a miss penalty of 20 clock cycles, a miss rate of 0.05 miss sses per er instru uction, and a cache ac access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the sarre and ignore other write stalls.

4.7 Suppose that in 1000 memory references, there are 40 misses in the first-level cache and 20 misses in the second-1 level cache. Assume the miss pen nalty from L2 cache to memo ory is 200 clock cycles, the hit time of L2 cache is 10 clock cycles, and the hit time of Ll cache is 1 clock cycle. What is the average memory y access time? Hint: average memory access time = LI_hit_time + Ll miss rate * ( 12 hit time + L2 local_miss_rate * * L2 miss penalty ) where the 12 local miss_rate is the nunber of misses in L2 cache divided by the total numnber of memory accesses to L2 cache.

4.8 Continued with the previous problem, and assuming that there is 1.5 memory references per instruction, what are the average stall cycles per instructions? Hint: average memory stall pet instruction = Ll_misses _per_instruction L2 hit time + L2 misses per _instruction 12 _miss_penaity

5. 5.1 What is the advantage of single instruction multiple data (SIMD)? Compare the differences between SIMD in conventional CPU (Central Processing Units) and SIMD in GPU (Graphics Processing Units)

5.2 What is control hazard? Propose a method to improve the performance degradation due to control hazard.

5.3 What are the differences of spatial locality and temporal locality during execution of computation tasks in CPU? Give two programming techniques to explain the differences.

5.4 What is static multiple issue? What is dynamic multiple issue? Compare the differences.