5.2 Assume N instructions are on the correct path of a program and assume a branch predictor accuracy of A. Write the equation for the number of instructions that are fetched on this machine in terms of N and A.

4.1What is the hit rate of the TLB for this sequence of references?

4.2 At the end of this sequence, what three entries are contained in the TLB?

4.3 What are the contents of the 8 physical frames?

5.1 How many instructions of wasted work are there per branch misprediction on this machine?

5.3 If the machine were modified so that it used the dual path execution (where an equal number of instructions are fetched from each of the two branch paths). Assume that branches are resolved before new branches are fetched. Write how many instructions would be fetched in this case as a function of Empty Page 2

6. A byte-addressable system with 16-bit address ships with a three-way set associative, write-back cache. The cache implements a true LRU replacement policy using the minimum number of replacement policy bits necessary to implement it. The tag store requires a total of 264 bits of storage. What is the block size of the cache?

7. A byte-addressable processor is connected to a single memory channel that has a singlerank of DRAM. The physical address space is 32 bits, and the processor uses the following mapping shown in Table 3, to index the DRAM. Each DRAM row has a certain number of columns, where acolumn has the same size of a cache line. The processor uses 64-byte cache lines. The Columns is 6bits and the Cache Line Offset is also 6 bits. In addition, the row size is 4 KB.Table 3 Mapping from the physical address to DRAMTable 4 shows the memory request queue that has 4 pending memory request at time 0.Assuming thatA row buffer hit takes 50 cyclesA row buffer conflict takes 250 cycles.Requests going to different banks can be processed by the banks in parallel.All the row buffers are closed at times 0.The controller cannot issue two requests at the same time. Each request takes 10 cycles to process,so it takes 10 cycles between issuing two separate requests to the memory.The controller employs First Ready-First Come First Serve (FR-FCFS) scheduling policy.Table 4. the state of the memory request queue at time 0.If it takes 320 cycles to finish processing all four requests in the memory, at least how many banks does this rank of DRAM have?

8.1Give two disadvantages of static code scheduling.

8.2Give two disadvantages of dynamic code scheduling.

8.3What are two mechanisms that dynamic code scheduling uses to mitigate the shortcomings of static code scheduling, and why does each mechanism help?