5.2 What is control hazard? Propose a method to improve the performance degradation due to control hazard.

4.6 Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%. If 100 cycles for all misses, de etermine how m a processor has a CPI (cycle per instruction) of 2 without any memory stalls and the miss penalty is much faster a proce cessor would run with a perfect cache that never missed. Assue the frequency of all loads and stores is 36%.

4.7 Suppose that in 1000 memory references, there are 40 misses in the first-level cache and 20 misses in the second-1 level cache. Assume the miss pen nalty from L2 cache to memo ory is 200 clock cycles, the hit time of L2 cache is 10 clock cycles, and the hit time of Ll cache is 1 clock cycle. What is the average memory y access time? Hint: average memory access time = LI_hit_time + Ll miss rate * ( 12 hit time + L2 local_miss_rate * * L2 miss penalty ) where the 12 local miss_rate is the nunber of misses in L2 cache divided by the total numnber of memory accesses to L2 cache.

4.8 Continued with the previous problem, and assuming that there is 1.5 memory references per instruction, what are the average stall cycles per instructions? Hint: average memory stall pet instruction = Ll_misses _per_instruction L2 hit time + L2 misses per _instruction 12 _miss_penaity

5. 5.1 What is the advantage of single instruction multiple data (SIMD)? Compare the differences between SIMD in conventional CPU (Central Processing Units) and SIMD in GPU (Graphics Processing Units)

5.3 What are the differences of spatial locality and temporal locality during execution of computation tasks in CPU? Give two programming techniques to explain the differences.

5.4 What is static multiple issue? What is dynamic multiple issue? Compare the differences.

2. 2.1 A processor is busy with computation 40% of aputation 40% of the execution time, and is waiting for I/O access 60% of the execution time. If we replace the processor with a new one which is 10 times faster than the old processor, what is the overall speedup gained using the new processor assuming that the percentage of IO access remains the same in both processors?

(1) Explain the five possible states of a process.

(2) Explain two common models for inter-process communications.

(3) Let us consider five processes arriving in the order of P1, P2, P3, P4, and P5 at time O:Show the turnaround time of each process based on the following scheduling algorithms: First-come first-served, round robin (with quantum = 1), shortest job first, and non-preemptive priority(where a smaller priority number indicates a higher priority).