101年 - 101 國立交通大學_碩士班考試入學試題_資訊聯招：計算機組織#105750

選擇題 (10)

複選題

1. Consider a computer running a program with CPU times shown in the following table:
(A) If the time for FP instructions is reduced by 40%, the total execution time of the program reduced in percentage is 20%. (B) If the time for L/S instructions is reduced by 80%, the speedup of the program is 1.25. (C) If the speed of the INT instructions is improved to 3 times faster, this program may run 1.25 times faster. (D) This program may run 1.8 times faster by improving the speed of FP instructions.

複選題
2.Which of the following statements are correct? (A) The dynamic power dissipation of CMOS is proportional to the square of the voltage applied. (B) Static power dissipation occurs because of leakage current that flows even when a transistor is off. (C) Computers at lower utilization use less power proportionally. (D) The main reason for the switch from high-performance uniprocessors to multiprocessors with simpler cores and lower clock rates in recent years is the power limit.

複選題

3. Given the IEEE-754 single precision floating-point operand format as follows,
(A) The decimal number -13.5 is represented as 1 10000011 11011000000000000000000 (B) The largest positive normalized number is (C) The smallest positive denormalized number is (D) Exponents with all 1's are reserved for ±∞ and NaN (Not a Number).

複選題
4. Multiply algorithm (A) For a multiplication with multiplier 1100101111100111, the traditional multiplication algorithm performs 11 additions for the product. (B) For a multiplication with multiplier 1100101111100111, Booth's algorithm performs 3 additions and 3 subtractions for the product. (C) Booth's algorithm requires less arithmetic operations than that of the traditional multiplication algorithm. (D) Booth's algorithm may be applied to two's complement multiplication.

複選題
5.Which of the following statements are correct? (A) For a fixed-size cache, miss rate will decrease as the block size increases. (B) Increasing block size can decrease compulsory miss. (C) For a two-level cache, the design of the primary (first-level) cache focuses on minimizing its miss rate, and the design of the second-level cache focuses on minimizing its hit time. utilizes (D) Fetching instructions in a loop temporal locality while sequential instruction access demonstrates spatial locality.

複選題
6. What instruction(s) below may fail to run correctly if the datapath labeled A in the single-cycle CPU figure has been cut ? (A) add (B) sw (C)lw (D) slt

複選題
7. What instruction(s) below may fail to run correctly if the control signal "RegDst" in the single-cycle CPU has been cut and stuck at 1? (A) add (B) sw (C) lw (D) slt

複選題

8. With single-cycle CPU, what control signal(s) below will be set to 1 when the code runs to the cycle? (A) RegDst (B) ALUSrc (C) MemToReg (D) Mem Write

複選題

9. With the pipelined CPU, what control signal(s) below will be set to 1 when the code runs to the cycle? (A) RegDst (B) ALUSrc (C) MemToReg (D) Mem Write

10. With the pipelined CPU, what control signal below will be set to 1 when the code runs to the cycle? (A) RegDst (B) ALUSrc (C) MemToReg (D) Mem Write

申論題 (16)

(1) Is it possible to use one single branch-on-equal (beq) MIPS instruction to get to address 0x0003 0000?

(2) Same to question (a) except that the address is changed to Oxffff ff00.

(3) Is it possible to use one jump (j) MIPS instruction to get to address 0x0003 0000?

(4) Same to question (c) except that the address is changed to Oxffff ff00.

(1) The pipelined CPU for which assume the forwarding mechanism has been designed and the branch outcome is determined at MEM stage.

(2) The pipelined CPU for which assume the forwarding mechanism has been designed and some hardware has been added to determine the branch outcome at ID stage.

(1) Which one(s) cannot have "small writes" to occur in parallel?

(2) Which one(s) cannot have "small reads" to occur in parallel?

(3) Which one has the best "small reads" latency?

(4) Which one is least tolerant to disk failure?

4. (8%) Assume the system workload consists of repeated reads of 64KB block at random disk locations. For the following system setup, (A) what is the IOPS (I/Os per second) for CPU, memory bus, and disk drive,respectively? (B) what (CPU, memory bus, or disk) is the bottleneck in the system?

●The user program uses 2 million cycles to process each I/O operation.
●The operating system requires 1 million cycles of overhead for each I/O operation.
●The clock rate is 3GHz.
●The maximum sustained transfer rate of the memory bus is 640MB/sec
●One disk drive which rotates at 7200RPM, has an average seek time of 8ms, and has a transfer rate of 64MB/sec. The disk controller overhead is 2ms.
Express your answer as the following table

5. (8%) A processor and two options for improving its hardware and compiler design are described as follows:

6.(6%) Given the block diagrams of a 32-bit ALU, the typical 1-bit ALU, and the 1-bit ALU for the most
significant bit (MSB), determine the values of control and carryin signals to perform each of the following operations:
NOR: Result = (A OR B)'
SUB: Result = A - B
SLT: If A ＜B. Result = 1； else Result = O

(1) Determine the numbers of bits for Tag and Index fields in the address format if the cashe is direct-mapped, 4-way set-associative, fully associative. Express your answer as Column (A) in the following table.

(2)Determine the size of a block (including valid bit, dirty bit, tag, and data) in bits if the cashe is direct mapped and the size of a set (including valid bit, dirty bit, tag, and data) in bits if the cashe is 4-way set-associative and fully associative. Then, calculate the total size in Kbits for each of the cashe configurations. Express your answer as Column (B) in the following table.

(3)Give a series of byte references in hexadecimal as shown in the following table.4-way set-associative cache, determine the tag and index of each reference in hexadecimal and label each reference as a hit or a miss. Assume that the cache is empty initially and LRU replacement is adopted. Express your answer as the following table.

101年 - 101 國立交通大學_碩士班考試入學試題_資訊聯招：計算機組織#105750

試卷資訊

選擇題 (10)

申論題 (16)