103年 - 103 國立中山大學_碩士班招生考試_資工系(甲、乙組)：計算機結構#105837

科目：中山◆資工◆計算機結構 | 年份：103年 | 選擇題數：0 | 申論題數：25

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所屬科目：中山◆資工◆計算機結構

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申論題 (25)

(a) Given a program with 10 instructions divided into classes as follows: 10% class A, 20% class B. 50% class C, and 20% class D, which implementation is faster?

(b) What is the global CPI for each implementation?

2.(a)

(b) Convert the decimal number -320 into signed 10-bit binary number in the 2's complement representation.

(c) Assume that signed numbers are stored in 10-bit words in 2's complement representation. What is the result of ?

(d) Show the IEEE 754 binary representation of the number in single precision.

(a) A multi-core processor consists of multiple chips, each containing a processor.

(b)A server is a computer composed of hundreds to thousands of processors and terabytes of memory.

(c)Acces ess time to random access memory (RAM) is longer than access time to hard disk.

(d)Assembly language consists of commands that processors understand.

(e)The application software is software/programs developed by the users.

(1)NaN in IEEE 754 can be the result of dividing 0 by 0 (0/0).

(a) How many times is instruction memory accessed? How many times is data memory accessed? (Count only accesses to memory, not registers.)

(b) What are the addressing modes used in the four instructions?

(a) What is the clock cycle time if the only types of instructions we need to support are ALU instructions (ADD, AND, etc.)?

(b) What is the clock cycle time if we only have to support LW (load word) instructions?

(e) What is the clock cycle time if we must support ALU, branch, load/store instructions? (Hint: You need to find the overall latencies of the blocks in the longest path required to execute an instruction.)

(a) What is the clock cycle time in a pipelined and non-pipelined processor?

(b) What is the total latency of an LW instruction in a pipelined and non-pipelined processor? (5%)

(a) Indicate dependences and their type.

(b) Assume there is no forwarding in this pipelined processor. Indicate hazards and add NOP instructions to eliminate them.

(a) Consider a direct-mapped cache with 16KB of data and 16-byte blocks, assuming a 32-bit 300ps address. What is the length of the tag field? How many total bits are required, assuming a valid bit is used?

(b) Assume an instruction cache miss rate for gcc of 2% and a data cache miss rate of 4%. If a machine has a CPI of 2 without any memory stalls and the miss penalty is 40 cycles for all misses, determine how much faster a machine would run with a perfect cache that never missed. Assume 36% of instructions are loads/stores.

(a) Page fault

(b) Direct memory access (DMA)