104年 - 104 國立中山大學_碩士班招生考試_資工系(甲、乙組)：計算機結構#105827

科目：中山◆資工◆計算機結構 | 年份：104年 | 選擇題數：0 | 申論題數：20

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所屬科目：中山◆資工◆計算機結構

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1.1 Using the average instruction mix information for the program SPEC2000fp, find the percentage of all memory accesses (both data and instruction) that are for reads. Assume that two- thirds of data transfers are loads.

1.2 Compute the effective CPI for MIPS. Average the instruction frequencies for SPEC2000int and SPEC2000fp to obtain the instruction mix.

1.3 Consider an architecture that is similar to MIPS except that it supports update addressing for data transfer instructions. If we run SPEC2000int using this architecture, some percentage of the data transfer instructions will be able to make use of the new instructions, and for each instruction changed, one arithmetic instruction can be eliminated. If 25% of the data transfer instructions can be changed, which will be faster for SPEC2000int, the modified MIPS architecture or the unmodified architecture? How much faster? (Assume that both architectures have CPI values as given in the above table and that the modified architecture has its cycle time increased by 20% in order to accommodate the new instructions.)

2.1 Using C1 on both Il and 12, how much faster can the makers of I1 claim Il is compared to I2?

2.2 Which computer and compiler would you purchase if all other criteria are identical, including cost?

3.1 What will the speedup be if both improvements are made?

3.2 You are going to change the program described in Problem 3 so that the percentages are not 20%, 50%, and 30% anymore. Assuming that none of the new percentages is O, what sort of program would result in a tie with regard to speedup (i.e., the same speedup) between the two individual improvements? Provide both a formula and some examples.

4.1 We have a program of 1000 instructions in the format of "Iw, add, 1w, add, .. ." The add instruction depends (and only depends) on the 1w instruction right before it. The 1w instruction also depends (and only depends) on the add instruction right before it. If the program is executed on the pipelined datapath of Figure 1, what would be the actual CPI?

4.2 What would be the actual CPI for the program in Problen 4.1 without forwarding?

4.3 Consider executing the following code on the pipelined datapath of Figure 1. How many cycles
will it take to execute this code?

4.4 With regard to the code in Problem 4.3, explain what the forwarding unit is doing during the sixth cycle of execution. If any comparisons are bcing made, mention them.

5.1 Always-taken

5.2 1-bit predictor (initialized to predict taken)

5.3 2-bit predictor as shown in Figure 2 (initialized to weakly predict taken)

6.1 Find the AMAT for a processor with a 2 ns clock, a miss penalty of 20 clock cycles, a miss ratc of 0.06 misses per instruction, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.

6.2 Suppose we can improve the miss rate to 0.04 misses per reference by doubling the cache sire. This causes the cache access time to increase to 1.2 clock cycles. Using the AMA'T as a metric, determine if this is a good trade-off.

6.3 If the cache access time determines the processor's clock cycle time, which is often the case, AMAT may not correctly indicate whether one cache organization is better than another. If the processor's clock cycle time must be changed to match that of a cache, is this a good tradc-off? Assume the processors are identical except for the clock rate and the number of cache miss cycles； assume 1.5 references per instruction and a CPI without cache misses of 2. The miss penalty is 20 cycles for both processors.

7.1 Assuming a cache of 16K blocks and a 32-bit address, find the total number of sets and the total number of tag bits for Cache I, Cache 2, and Cache 3.

7.2 Determine which processor spends the most cycles on cache misses.

7.3 The cycle times for the processors in Problem 7.2 are 400 ps for the first and second processors and 300 ps for the third processor. Determine which processor is the fastest and which is the slowest.