107年 - 107 國立中山大學_碩士班招生考試_資工系(甲、乙組)：計算機結構#105781

科目：中山◆資工◆計算機結構 | 年份：107年 | 選擇題數：0 | 申論題數：29

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所屬科目：中山◆資工◆計算機結構

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申論題 (29)

1.1 What is the CPI of your processor on this mix of instructions?

1.2 Based on your design, if you could halve the cycle latency of any single category of instruction, but at the cost of increasing the cycle time by 20%. Should you make this change, and if so, what category of instruction should you speed up? (load, store, branch, add, or divide)

1.3 What is the CPI of your new design?

1.4 What is the speedup of your revised design over the original one, rounded to the nearest tenth?

2.1 What specific positive impact would combining the "D" and "X"' stages have on CPI?

2.2 What specific positive impact would combining the "X" and "M" stages have on CPI?

2.3 What specific positive might combining the "M" and "W" stages have on the clock frequency of the pipeline?

2.4What specific impact would combining the "F" and "D' stages have on the implementation of branch prediction?

2.5 If a single-cycle datapath with delay of n nanoseconds is converted into a pipelined datapath with p stages, the clock period will be longer (slower) than n/p nanoseconds. Give two reasons for this.

3.1 What do VLIW, superscalar execution, and array processing concepts have in common?

3.2 Provide two reasons why a VLIW microarchitecture is simpler than a "same-width" superscalar microarchitecture?

3.3 Provide two reasons why a superscalar microarchitecture could provide higher performance than a "same-width" VLIW microarchitecture?

4.1 Associativity? (1, 2, or 4 ways)

4.2 Block size? (1,2,4,8, 16, or 32 bytes)

4.3 Total cache size? (256 bytes, or 512 bytes)

4.4 Replacement policy? (LRU, or FIFO)

5.1 Suppose you would like to connect 625 processors, and you are considering three different topologies: bus, point-to-point network, and mesh. Describe one disadvantage of each : (i) A single Bus (ii) A point-to-point network (iii) A 25x25 Mesh.

5.2 Which one of these three topologies would you choose to connect 625 processors? Why?

6.1 What is the number of tag comparators per reservation station entry?

6.2 What is the total number of tag comparators in the entire machine?

6.3 What is the (minimum possible) size of the tag?

6.4 What is the (minimum possible) size of the register alias table (or, frontend register file) in bits?

6.5 What is the total (minimum possible) size of the tag storage in the entire machine in bits?

7.1 If your program can perform 90% of its work (measured as processor-seconds) in the parallel portion and 10% of its work in the serial portion. The parallel portion is perfectly parallelizable. What is the maximum speedup of the program if the multicore processor had an infinite number of cores?

7.2 How many processors would be required to attain a speedup of 4?

8.1 How long does each refresh command occupy the command bus (in ns) such that across all memory channels, the command bus utilization due to refreshes is 8.192%? (Hint 8.192 = 213/1000)

8.2 How long does each refresh command occupy the DRAM banks (in ns) such that across all the banks, the banks utilization due to refreshes is 8.192%?

8.3 What data bus utilization, across all memory channels, is directly caused by DRAM refreshes?

8.4 How many refreshes are performed by the memory controllers during the 1.024 second period in total across both memory channels combined?