(a) by using only NOR and inverter gates. (5%)

(b)How to obtain the complement of a Boolean function?(2%) Give the complement of the Boolean function shown below. (2%) F(w, x, y,z) =xyt w'xz'tw'z'tx'yz.

(c) Give the 2's complement of 10110100 (2%) Give the signed 2's complement of"-8" using a total of eight digital bits (2%)

(d) What is RAM? (2%) What is ROM? (2%)

(e) What are the three states of a three-state logic gate such as a tri-state buffer? (3%)

(b) by using only AND and inverter gates. (5%)

(c)by using the simplest sun-of-products form (5%)

(d)by drawing the logic diagram using a multiplexer (5%) Please note that for (a), (b) and (c) you only need to show the final Boolean function and how you derive the function.

[Problem 3] (20%) 8-4-2-1 is a useful 4-bit binary code to represent decimal digits, as listed in Table 1. Design a combinational circuit F that can check if the decimal input encoded by 8-4-2-1 is an odd or even number. The output F of the circuit equals 1 if and only if the decimal input is an even number. Otherwise, F equals 0. You need to show the truth table of this circuit and design the two-level NAND- NAND network using the minimum number of logic gates and literals. Please note that the input code words (w, x, y, 2) and their complements can be used directly as fan-in in the final logic diagram, and the unused input code words can be used as don't care conditions for logic simplification.

Problem 4](20%) What are two common storage elernents in a sequential circuit? (4%) What are the differences between the operation conditions of these two elements? (4%) Give some waveforms to explain the meaning of the setup time and the hold time constraints in a synchronous sequential circuit. (6%) Give a general structure of a synchronous sequential circuit and use this structure to explain how the maximum operating frequency of a synchronous sequential circuit is determined. (3%) How can the maximum operating frequency be increased? 3%

(a) Give Verilog/VHDL codes of an asynchronously resettable positive edge-triggered flip-flop. (3%)