申論題

[Problem 4] (20%) A 2.0 GHz microprocessor runs a program of 1000 assembly instructions. Given the following assumptions: (i) all the instructions are 32-bit long and they all use immediate addressing mode; (ii) one memory location can accommodate one 32-bit instruction; (iii) an address or data bus cycle will take 2 CPU cycles; and (iv) address bus and data bus are both 16-6it wide. After an instruction is fetched fom memory to instruction register, it requires 1 cycle for instruction decoding, 2 cycles for instruction execution, and 1 cycle for storing the result to register. Assume no instruction pipelining is employed,compute

(b) (5%) CPI (Cycles per Instruction).