7.(25 pts) Consider a 5-stage (IF, ID, EX, MEM, WB) RISC-V pipelined processor (Figure 1) composed of logic blocks with the
following latency (any unspecified block latency is treated as O):
申論題內容
(c) (5 pts)When the sub instruction (#4) is in the EX state, what value should be set for the control signal ForwardA (c1) and
ForwardB (c2), respectively?
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