題組內容

2. (8%) In this problem, we examine how pipelining affects the clock cycle time of the processor. Assume the individual stages of the datapath have the following latencies:
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And, assume that instructions executed by the processor are broken down as follows:61bad33f7a8dd.jpg

(d) (2%) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? 300ps 100ps