7.(25 pts) Consider a 5-stage (IF, ID, EX, MEM, WB) RISC-V pipelined processor (Figure 1) composed of logic blocks with the
following latency (any unspecified block latency is treated as O):
申論題內容
(d) (5 pts) What are the control signal values for RegWrite (d1),MemtoReg(dz),MemRead(d3), and MemWrite (d4) for the sub
instruction?
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