(e) [4%] For Case I as the final state of the cache, how many valid entries in this cache? Show the index for each valid entry. Case I

(a) [3%] What is the block size (in words) of each case?

(b) [3%] For the total of two cases, how many entries does the cache have??

Starting from power on, the following byte-addressed cache references are recorded.(c) [3%] For Case I, how many blocks are replaced?

(d) [3%] For Case I, what is the hit ratio?

(a) [3%] Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%, If a processor has a CPI of 2 without any memory stalls and the miss penalty is 200 cycles for all misses. Assume the frequency of all loads and stores is 36%. Determine how much faster a processor would run with a perfect cache that never missed.

(b) [3%] If the processor has a base CPI of 1, and clock rate of 4 GHz. Assume the memory access time is 100 ns, including al the miss handling. Suppose the miss rate per instruction at the primary cache is 3%. Now we add a secondary data cache that has a 5 ns access time for either a hit or a miss, and is large enough to reduce the miss rate to main memory to 0.5%. What is the total CPI of this two-level cache?

(a) [3%] For a single-level page table, how much physical memory is needed for storing the page table?

(b) [3%] In a memory hierarchy system, we can integrate virtual memory, TLB and cache. A memory reference can encounter three different types of misses: a TLB miss, a page fault and a cache miss. Considering all the combinations of these three events with one or more occurring. Identify the number for the three events which is impossible.

Problem 1.  Given a matrix   where a is a real numnber. Find the rank of A1 and give the corresponding range of a.

(i)  Find the Eigenvalues and Eigenvectors for.