申論題

[Problem 5] Use the following code fragment:

Loop:
     Assume the initial value of R3 is R2+200. Use the five-stage instruction pipeline ( IF, DEC, EXE, MEM, WB) and assume all memory accesses are one cycle operation. Furthermore, branches are resolved in MEM.
    Show the timing of this instruction sequence for the five-stage instruction pipeline with normal forwarding and bypassing hardware. 

    Assume that branch is handled by predicting it has not taken. How many cycles does this loop take to execute? (10%) Assuming the five-stage instruction pipeline with a single-cycle delayed branch and normal forwarding and bypassing hardware, schedule the instructions in the loop including the branch- delay slot. You may reorder instructions and modify the individual instruction operands, but do not undertake other loop transformations that change the number of op-code of instructions in the loop. Show a pipeline timing diagram and compute the number of eyeles needed to execute the entire loop. (15%