3. For the circuit shown in Fig. Problem 3, find the values of R2 and C to
yield 8% overshoot with a settling time of I ms for the voltage across
the capacitor, with vi(t) as a step input. (25%)
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3. For the circuit shown in Fig. Problem 3, find the values of R2 and C to
yield 8% overshoot with a settling time of I ms for the voltage across
the capacitor, with vi(t) as a step input. (25%)