申論題

4.(40%) You are a system engineer. Today, you need to design a memory hierarchical system, including one CPU, one or two-level cache, one main memory, and one hard disk. Currently, you have the following design policies for the cache-level design.
 Poliey 1: With only L1 cache by using 2-way associativity
Policy 2: With direct mapping L1 cache and 2-way associative L2 cache
 Policy 3: With 2-way associative L1 and L2 caches
Assume that there is one embedded TLB in each cache level and one embedded page table in the main memory (i.e., we do not need extra memory to store the TLB and page table). On the other hand, the specifications of this memory hierarchical system are
■This is a 32-bit machine.
■The base CPI is 1.0 and the clock rate is 5GHz.
■ Each cache block is a single-word block.
■The L1cache can contain 8KB data.
■The L2 cache can contain 16KB data.
■The page size is bytes.
■ In the TLB and page table, we need to involve an extra one dirty bit to implement the write-back policy； one reference bit to approximate the LRU replacement policy； one valid bit to judge the data hit/miss.
■The number of the TLB entries in L1 and L2 caches are 10 and 20 respectively. Besides, the number of entries in the page table is 30. To reduce the miss rate, the fully associative policy is adopted to implement the TLB and page table.

4.3 (20%) Without considering the data transferring time, we assume the access time of L2 cache is 5 ns including all the miss handling； the access time of the main memory is 100 ns including all the miss handling； the access time of the hard disk is 1 us including all the miss handling. According to the data transference time between each memory level, we ignore the data transference time between the L1 and L2 cache and the data transference time between the main memory and the lowest level cache and disk are both 50 ns ineluding all the miss handling. In this system, the TLB will be located at the lowest level cache. When a data request comes, the TLB must be accessed first. If the TLB miss happens, we need to spend ions to handle the TLB-miss exception. When we adopt direct mapping strategy, the miss rate of the L1 cache and the embedded TLB are both 2%； the miss rate of the L2 cache and the embedded TLB are both 0.5%. If the 2-way mapping strategy is applied, the miss rate of the L1 cache and the embedded TLB are both 1%； the miss rate of the L2 cache and the embedded TLB are both 0.1%. At last, the miss rate of the main memory is 0.1%. During manufacturing, we need to spend 0.01 USD to handle one bit in each kind of memory. Please provide a design suggestion, including how many cache level you suggest and what kind of mapping strategy for each cache level you suggest, to your customer by considering the system performance and the manufacturing simultaneously cost.