4.1 How nuny bits in toteal (including the tag bits and vaid bite) are reqvired for dlue tt aor cache with 16K bytes of data and 16-byte blocks, assuming a 32-bit address and one valid bit for each cache block?
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4.4 Compare the advantages and disadvantages of the above three different cache designs. Which one is usually used in the design of TLB (translati ation lookaside buffer)? Why?
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