4.1 How nuny bits in toteal (including the tag bits and vaid bite) are reqvired for dlue tt aor cache with 16K bytes of data and 16-byte blocks, assuming a 32-bit address and one valid bit for each cache block?
申論題內容
4.5 The average mem mory access time (AMAT) per instruction can be expressed as
AMAT = time for a hit + miss rate *miss penalty
Find the AMAT for a processor with a 1ns clock cycle time, a miss penalty of 20 clock cycles, a miss
rate of 0.05 miss sses per er instru uction, and a cache ac access time (including hit detection) of 1 clock cycle.
Assume that the read and write miss penalties are the sarre and ignore other write stalls.
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