4.1 How nuny bits in toteal (including the tag bits and vaid bite) are reqvired for dlue tt aor cache with 16K bytes of data and 16-byte blocks, assuming a 32-bit address and one valid bit for each cache block?
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4.6 Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%. If
100 cycles for all misses, de etermine how m
a processor has a CPI (cycle per instruction) of 2 without any memory stalls and the miss penalty is
much faster a proce cessor would run with a perfect cache that
never missed. Assue the frequency of all loads and stores is 36%.
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