19 下圖中所含的最小擴張樹（minimal spanning tree）其各邊為何？ (A)(0,1),(0,2),(1,3),(3,5),(3,2),(1,4) (B)(0,2),(2,3),(2,4),(4,5),(1,4) (C)(0,1),(0,2),(1,3),(3,5),(5,4) (D)(0,1),(1,3),(3,2),(1,4),(3,5)

19 下圖中所含的最小擴張樹（minimal spanning tree）其各邊為何？

(A)(0,1),(0,2),(1,3),(3,5),(3,2),(1,4)
(B)(0,2),(2,3),(2,4),(4,5),(1,4)
(C)(0,1),(0,2),(1,3),(3,5),(5,4)
(D)(0,1),(1,3),(3,2),(1,4),(3,5)

答案：登入後查看
統計： A(31), B(32), C(45), D(210), E(0) #682773

詳解 (共 1 筆)

Ai Ping Chen

B1 · 2020/03/16

#3829039

最小生成樹其實是最小權重生成樹的簡稱。 ...

(共 297 字，隱藏中）

前往觀看

5 若欲使用 Verilog 語言合成（synthesize）出與下圖相同功能的電路，則下列各 Verilog 模組何者正確？ (A)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; reg Y;always @(posedge clock) X <= A | B;always @(B or C) Y = B & C; endmodule (B)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; reg Y;always @(posedge clock) X <= A | B;always @(posedge clock) Y = B & C; endmodule (C)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; wire Y;always @(posedge clock) X = A | B;always @(posedge clock) Y = B & C;endmodule (D)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; reg Y;always @(posedge clock) X <= A+B;always @(B or C) Y = B * C;endmodule D X Y A B C clock

19 下圖中所含的最小擴張樹（minimal spanning tree）其各邊為何？
(A)(0,1),(0,2),(1,3),(3,5),(3,2),(1,4)
(B)(0,2),(2,3),(2,4),(4,5),(1,4)
(C)(0,1),(0,2),(1,3),(3,5),(5,4)
(D)(0,1),(1,3),(3,2),(1,4),(3,5)

詳解 (共 1 筆)

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