3 下列何者為八進位數(42)8與八進位數(24)8相減的結果？ (A)(18)8(B)(16)8(C)(14)8(D)(12)8

3 下列何者為八進位數(42)₈與八進位數(24)₈相減的結果？
(A)(18)₈
(B)(16)₈
(C)(14)₈
(D)(12)₈

答案：登入後查看
統計： A(149), B(788), C(58), D(30), E(0) #682757

詳解 (共 2 筆)

Rachel Hong

B2 · 2017/01/27

#1601651

八進位最大數值為8

個位數2不夠4減，向10位借

=8-4=4+2=6

4-2-1=1

答案=16

u9831049

B1 · 2015/08/09

#1131677

求解

5 若欲使用 Verilog 語言合成（synthesize）出與下圖相同功能的電路，則下列各 Verilog 模組何者正確？ (A)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; reg Y;always @(posedge clock) X <= A | B;always @(B or C) Y = B & C; endmodule (B)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; reg Y;always @(posedge clock) X <= A | B;always @(posedge clock) Y = B & C; endmodule (C)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; wire Y;always @(posedge clock) X = A | B;always @(posedge clock) Y = B & C;endmodule (D)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; reg Y;always @(posedge clock) X <= A+B;always @(B or C) Y = B * C;endmodule D X Y A B C clock

3 下列何者為八進位數(42)₈與八進位數(24)₈相減的結果？
(A)(18)₈
(B)(16)₈
(C)(14)₈
(D)(12)₈

詳解 (共 2 筆)

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