27 下列各 C 語言函式宣告中，何者錯誤？ (A)double fn(void); (B)float fn(a,b,c,d); (C)double fn(int,double,float); (D)int fn(int a,double b,float);

27 下列各 C 語言函式宣告中，何者錯誤？
(A)double fn(void);
(B)float fn(a,b,c,d);
(C)double fn(int,double,float);
(D)int fn(int a,double b,float);

答案：登入後查看
統計： A(35), B(79), C(35), D(46), E(0) #682781

詳解 (共 1 筆)

Phil(112高普雙榜)

B1 · 2020/07/07

#4122347

選項B不行是因為宣告的值必須要有型態，直...

(共 176 字，隱藏中）

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5 若欲使用 Verilog 語言合成（synthesize）出與下圖相同功能的電路，則下列各 Verilog 模組何者正確？ (A)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; reg Y;always @(posedge clock) X <= A | B;always @(B or C) Y = B & C; endmodule (B)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; reg Y;always @(posedge clock) X <= A | B;always @(posedge clock) Y = B & C; endmodule (C)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; wire Y;always @(posedge clock) X = A | B;always @(posedge clock) Y = B & C;endmodule (D)module TestCircuit (A, B, C, clock, X, Y);input A;input B;input C;input clock;output X;output Y;reg X; reg Y;always @(posedge clock) X <= A+B;always @(B or C) Y = B * C;endmodule D X Y A B C clock

27 下列各 C 語言函式宣告中，何者錯誤？
(A)double fn(void);
(B)float fn(a,b,c,d);
(C)double fn(int,double,float);
(D)int fn(int a,double b,float);

詳解 (共 1 筆)

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