申論題

Problem 3: (20 points) Consider the following sequential circuit. Assume that the four D-flip-flops are triggered by the same clock signal, the flip-flop propagation delay is 1 ns, the flip-flop setup cime is 2 ns, the input signal X has delay 2 ns, the OR gate has delay 3 ns, and the XOR gate has delay 4 ns.