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102年 - 102 國立中山大學_碩士班招生考試_電機系(丙、己組)：計算機結構#110031
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[Problem 1] Terminology Explanation (20%) (a) Superscalar Processor (b) Pipeline Processing (c) Real Time Processing(d) Delayed branch (e) Multi-core Processor
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1. 品管圈
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2. 全面品質管制與全公司品質管制
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3. 管制循環 PDCA
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4. 管制中心線
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(a) Describe the floating-point addition algorithm and hardware for TEEE 754 standard.(10%)
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(b)Design the adder architecture for adding two IEBE 754 floating-point numbers with the nommalization form result. (10%)
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[Problem 3] A set associative cache has a block size of four 32-bit words and a set size of 4. The cache can accommodate a total of 64K words. The main memory size that is cacheable is 256M * 32 bits. Design the cache structure and show how the processor' s addresses are interpreted. (20%)
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[Problem 4] Briefly describe what three techniques are possible for I/O operations. (10%)
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(a)Given the instruction architecture as follows. (20%)Transfer the C program block as follows to the machine code as you can. (Assume: Start address of 32-bit integer array A--＞ 0x1000, Start address of 32-bit integer variable k- -＞ 0x1100 and Start address of 32-bit integer variable i -＞ 0x1104)
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(b) Suppose we have made the following measurements of average CPI for instructions: Compute the effective CPI for the machine code at(a). (10%)
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