(a) [5%] Explain the functions of the five pipeline stages of the pipelined MIPS CPU, respectively.

(a) [5%] Explain in detail how the architecture shown in Figure 1 is used to execute an I-type instruction (e.g., addi $s3, $s3, 1) step-by-step.

(b) [5%] Explain in detail how the architecture shown in Figure 1 is used to execute a jump instruction (e.g., j Ll) step-by-step.

(c) [5%] Describe in detail how this architecture is used to execute a load instruction (e.g., Iw $t0, 32($s3) ) step-by-step.

(d) [5%] Explain in detail how the architecture shown in Figure 1 is used to execute a branch instruction (e.g., beq $t0, $s5, Exit) step-by-step.

(b) [6%] Use examples to explain the three types of hazards of the pipelined MIPS CPU, respectively.

(c)[9%] Explain in detail how we can solve the three types of hazards of the pipelined MIPS CPU based on the architecture shown in Figure 2, respectively.

(a) [4%] Explain what two localities of memory data are and give examples, respectively.

(b) [2%] Explain how a hierarchical memory system takes advantage of localities.

(c)[4%] What are the advantages and disadvantages of SRAMs and DRAMs, respectively? How are they used in a hierarchical memory system, respectively?

(d) [15%] For a cache with 4 blocks, complete the cache access results for a direct mapped cache, a 2-way set associative cache and a fully associative cache, respectively, shown in the three tables shown below. Please draw these three tables in your answer papers and fill in your answers. Note that in this problem the least recently used block replacement policy is assumed. 請特別注意!請將第三頁表一、表二、 表三的內容繪製在答案卷中並填入答案才允予 計分。填寫在題目卷上將不予計分。