(a) [5%] Represent X and Y using IEEE 754 single precision format, respectively

4. Answer the following questions about MOS capacitor. (a) Explain the flat-band voltage. (5%)( b) Consider a n+polysilicon-SiO2-Si capacitor with a p-type silicon substrate doped to NA = cm, a silicon dioxide insulator with a thickness of 300 . The metal-semiconductor work function diference is -0.98 V. The fixed charge within the SiO2-Si interface Q/q = 4✖The dielectric constant of SiO2 is 3.9. Calculate the flat-band voltage. (15%)

5. For DRAM operation, assume that we need a minimum of 105 electrons for the MOS storage capacitor. The capacitor has an area of 0.6 μmx 0.6 um on the wafer, an oxide thickness of 7 nm, and is fully charged to 3 V. What is the required minimum depth of a rectangular-trench capacitor?

(a) positive photoresist and negative photoresist (5%)

(b) evaporation and sputtering (5%)

(b) [5%] Add X and Y, and represent the result using IBEE 754 single precision format

(c)5%] Multiply X and Y, and represent the result using IEEE 754 single precision format

2.[20%] Translate the following C code to the minimum MIPS assembly instructions  At the beginning of this code segment, the only values in registers are the base address of arrays A and B in registers $a1 and $a2. Assume that the values of i is stored in the register $s0

(a) [5%] Explain in detail how the architecture shown in Figure 1 is used to execute an I-type instruction (e.g., addi $s3, $s3, 1) step-by-step.

(b) [5%] Explain in detail how the architecture shown in Figure 1 is used to execute a jump instruction (e.g., j Ll) step-by-step.

(c) [5%] Describe in detail how this architecture is used to execute a load instruction (e.g., Iw $t0, 32($s3) ) step-by-step.