(Problem 3] (20%) A set associative cache has a block size of four 32-bit words and a set size of 4. The cache can accommodate a total of 256K words. The main memory size that is cacheable is 1024M * 32 bits. Design the cache structure and show how the processor's addresses are interpreted.

[Problem 5] Use the following code fragment:Loop: Assume the initial value of R3 is R2+200. Use the five-stage instruction pipeline ( IF, DEC, EXE, MEM, WB) and assume all memory accesses are one cycle operation. Furthermore, branches are resolved in MEM. Show the timing of this instruction sequence for the five-stage instruction pipeline with normal forwarding and bypassing hardware. Assume that branch is handled by predicting it has not taken. How many cycles does this loop take to execute? (10%) Assuming the five-stage instruction pipeline with a single-cycle delayed branch and normal forwarding and bypassing hardware, schedule the instructions in the loop including the branch- delay slot. You may reorder instructions and modify the individual instruction operands, but do not undertake other loop transformations that change the number of op-code of instructions in the loop. Show a pipeline timing diagram and compute the number of eyeles needed to execute the entire loop. (15%

(Problem 3] (20%) A set associative cache has a block size of four 32-bit words and a set size of 4. The cache can accommodate a total of 256K words. The main memory size that is cacheable is 1024M * 32 bits. Design the cache structure and show how the processor's addresses are interpreted.

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