(b) [4%] Why do we need valid bits and dirty bits in cache designs?

1. [20%] Translate the following C code to the minimum MIPS assembly instructionsint A[20], B[20]；i=0；while (A[i]!=0 && i＜20){B[i] = A[i]+B[A[i]]+i；i++；}At the beginning of this code segment, the only values in registers are the base address of arrays A and B in registers $al and $a2. Assume that the value of i is stored in the register $t1.