題組內容

(Problem 5](20%) Design an asynchronously resettable positive edge-triggered finite state machine that has two one-bit input a and b, and one output y. y equals I if a = b during any five cycles. Otherwise, y equals 0. For example, 
a:01101101001011001 
b:01001101101011000 
y:00000001000001110

(d)Write RTL Verilog/VHDL codes to implement the finite state machine you designed. (8%)