4. (15%) For a static four-input NAND gate with L a 0.18 um, all transistor sizes are chosen to match the delay of a basic CMOS inverter with (W/L)n = n and (W/L)p= p.
申論題內容
(b) (6%) For a static four-input NAND gate with n = 1.5 and p = 3, please give the sizes (W/L) of all transistors.
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