(c) Repeat (b), i.c., write down , for an Al/ SiO₂ /n -Si structure, albeit with N_A replaced by N_D. Denote again the metal work function asΦ_M and express the work function of Si in tem of . (6%)

Diodes and BJT 3.Please qualitatively plot the steady-state depletion region widths and the minority carrier concentration profiles in a pn junction under forward bias, zero bias, and reverse bias. Assume that the p-type doping concentration is larger than that of n-type. (15%)

4.The common-base current gain a of an NPN BJT can be expressed as a = γaTδ where a is the emitter injection efficiency factor, aT  is the base transport factor, andδ is the recombination factor. To have an a as large (close to 1) as possible, cach of these factors must be close to l as well. For these three factors, respectively, what about device design and/or operation bias must be done to make them large? (15%) If is increased, will a increase or decrease? Why? (5%)

(a) Given that the work function of the Al is slightly larger than , the electron affinity of Si, and assumed that the oxide is perfect (completely insulating, no fixed charge/interface states within the oxide and at the interface), please plot the band diagrams of the MOS capacitor when the MOS capacitor is biased at equilibrium and threshold, respectively. You have to include (vacuum level), Ec (conduction band edge), Ei (intrinsic level) , Ev (valence band edge) and EF (Fermi level) in you plots. Please also indicate on you plot the condition that the MOS structure reaches threshold. (10%)

(b) Denote the work function of Al as ΦM. If there is now fixed charges density (per unit area) (QF) at the SiO2/Si interface, write down, without derivation, the threshold voltage for the MOS capacitor. Note that you have to express the work function of Si in term of. (6%)

(d) Explain the difference between enhancement type and depletion type, for both n-channel MOSFET and p-channel MOSFET, in term of threshold voltage. If the Al / SiO2 / p - Si MOS structure in (a) is part of an MOSFET, is this MOSFET enhancement type or depletion type? Repeat for the Al / SiO2 /n- Si MOS structure in (c). (3%, 2%,2%)

(c) Please explain what CMOS logics are and their advantages over p-MOS/n-MOS technology for VLSIs of high integration level. (6%)

(a) (2%) Stall cycles due to mispredicted branches increase the CPI. What is the extra CPI due to mispredicted branches with the always-taken predictor? Assume that branch outcomes are determined in the EX stage, that there are no data hazards, and that no delay slots are used.

(b) (2%) Repeat (a) for the "'always-not-taken" predictor.

(c) (2%) Repeat (a) for the 2-bit predictor.

(d) (2%) With the 2-bit predictor, what speedup would be achieved if we could convert half of the branch instructions in a way that replaces a branch instruction with an ALU instruction? Assume that correctly and incorrectly predicted instructions have the same chance of being replaced.